As the semiconductor industry pushes the performance boundary of CMOS for the increasing circuit capability (i.e., reduction of channel resistance and power consumption, and increase in drive current, frequency response and operating speed), transistor architectures have turned to increased built-in mechanical channel stress to enhance carrier mobility. As known in the art, stress layers can increase electron mobility in the channel for n-metal oxide semiconductor field effect (n-MOS) devices and hole mobility in the channel for p-MOS devices. For a n-MOS device, tensile stress is induced by a stress layer, such as an epitaxial silicon-carbon (e-SiC) layer, that can cause the mobility of electrons to increase. On the other hand, when the CMOS device is a p-MOS device, the compressive stress caused by an e-SiGe can cause the mobility of the holes to increase.
The stress layer may be positioned in various locations relative to the channel of the device. In one arrangement, the channel stress is increased by forming source/drain recesses and epitaxially depositing alloyed silicon in the recesses. To achieve maximum effect, the stress inducing regions need to be close to the channel region of the devices. However, stress layer proximity is known to result in problems including an increase in device leakage in the off-state so that a maximum or near maximum stress effect is not realizable.